Senior Design Verification Engineer - IP

Company Overview: Advanced Micro Devices (AMD) is a multinational semiconductor company that provides high-performance computing solutions. Located in Bangalore, India, AMD is focused on innovation and collaboration.

Role Overview

The Senior Design Verification Engineer (IP DV) will be tasked with verifying complex, reusable High-Performance Computing (HPC) IP blocks for various System on Chip (SoC) programs. This position emphasizes ownership of IP-level verification, requiring a deep understanding of protocols, micro-architecture, and the ability to create reusable verification environments that can be integrated into larger SoCs. The role also incorporates AI-assisted verification techniques to enhance productivity and verification quality.

Experience Level

This position is suitable for professionals with 4-6 years of hands-on Design Verification experience, primarily at the IP level.

Key Responsibilities

• Own the functional verification of HPC-class IPs from specification review to sign-off.
• Develop thorough IP verification plans including corner cases, stress tests, and error scenarios.
• Create reusable SystemVerilog/UVM-based verification environments for performance-critical IPs.
• Design UVM agents, sequences, scoreboards, and coverage models to align with IP reuse goals.
• Create directed and constrained-random tests to validate IP functionality and protocol compliance.
• Drive coverage closure at the IP level including functional, code, and assertion coverage.
• Perform detailed debugging of RTL and testbench issues while collaborating with IP designers.
• Implement AI-assisted verification techniques to boost efficiency and effectiveness.
• Maintain clean, reusable, and well-documented verification collateral.
• Review specifications and RTL for verification completeness.
• Support handoff and integration efforts by SoC verification teams.
• Mentor junior engineers and advocate best practices, including productivity-enhancing tools.

Requirements

• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, or related field.
• 4–6 years of hands-on Design Verification experience at the IP level.
• Strong expertise in SystemVerilog and UVM methodology.
• Solid understanding of digital design and micro-architecture concepts.
• Proven experience with assertion-based verification (SVA).
• Strong knowledge of functional and code coverage techniques.
• Experience with verifying configurable, reusable, HPC-class IPs.
• Strong debugging skills with industry simulators (VCS, Xcelium, Questa, etc.).

Education Requirements

At least a Bachelor’s degree or higher in Electronics, Electrical Engineering, or a closely related field is mandatory.