Senior ASIC RTL Design Engineer

Role Summary

This position requires a Senior ASIC RTL Design Engineer to participate in cutting-edge design work, engaging collaboratively with teams across architecture, design, and product engineering.

Experience Level

This role is suitable for professionals with extensive experience in digital design and ASIC development, ideally at a senior career level.

Responsibilities

• Design RTL for high-speed circuits and handle power management features.
• Optimize designs for power efficiency using low-power techniques.
• Resolve inter-IP integration issues and manage clock-domain crossing.
• Collaborate with various engineering teams to integrate feedback into designs.
• Document and drive tasks to completion with a commitment to innovation.

Requirements

• Significant experience in Digital IP/ASIC design and Verilog RTL development.
• Knowledge of the full IP design cycle and familiarity with RTL design verification.
• Strong skills in EDA tools and low power design methodology are preferred.
• Proficient in programming with scripting languages such as Python or Perl.
• Excellent communication and organizational skills.

Education Requirements

Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.