Senior ASIC Digital Design Engineer - DFT

Role Summary

The Senior ASIC Digital Design Engineer specializes in Design for Test (DFT) with a focus on improving the reliability and quality of digital designs. You will be part of a dedicated engineering team working on innovative solutions within the semiconductor industry.

Experience Level

This position requires a minimum of 2 years of relevant experience in DFT, particularly in aspects like SCAN insertion and ATPG simulation.

Responsibilities

Your core responsibilities will include:

• Define and implement DFT architecture for IP designs.
• Conduct SCAN insertion and ATPG simulations to verify design testability.
• Analyze existing designs to enhance test coverage and efficiency.
• Develop timing constraints for DFT in Static Timing Analysis (STA).
• Prepare guidelines for DFT integration within System on Chip (SoC) designs.
• Perform quality checks alongside FMEDA/DFMEA analysis to ensure design robustness.

Requirements

Applicants should possess the following qualifications and skills:

• BS/MS/PhD in Electronics or a related field.
• A minimum of 2 years of experience in DFT design.
• Familiarity with Scan insertion, ATPG, and JTAG.
• Proficiency with Synopsys tools including Design Compiler, VCS, and TetraMAX.
• Ability to script in languages such as Perl, TCL, or Python is advantageous.

Education Requirements

A degree in Electronics or a related field is required, with a preference for candidates holding advanced degrees.