RTL Design Engineer

Role Summary

The AMD IOHUB Team is seeking an ASIC Design Engineer to develop I/O connectivity and virtualization technologies for data centers and machine learning workloads. This team works on the design of client, server, embedded, graphics, and semi-custom chips. The role encompasses all aspects of IP design from architecture to implementation.

Experience Level

Mid-Career

Responsibilities

• Understand the functional and performance requirements of the IOHUB within various SOCs.
• Drive IP/SOC design infrastructure decisions.
• Guide and liaise between IP and SOC design teams regarding synthesis and physical layout issues.
• Scope requirements and resources to meet project schedules.
• Lead a small team of Engineers in meeting program development goals.
• Ensure IP quality for delivery into SOC.
• Communicate effectively with multi-disciplined global teams.
• Present technical status updates during meetings.

Requirements

• Proven ASIC and RTL design experience, particularly on large development projects.
• Strong background in industry standard synthesis tools and flows.
• Proficiency in Verilog and System Verilog.
• Strong analytical skills with attention to detail.
• Excellent written and verbal communication skills.
• Knowledge of IP integration and interactions within SOCs.
• Self-starter capable of independently driving tasks to completion.
• Strong problem-solving skills.
• Demonstrated leadership capabilities.

Requirements

• Bachelor of Science in Electrical Engineering, Computer Science, or Computer Engineering.

Location

Vancouver, BC / Markham, ON