RTL Design Engineer

Role Summary

Collaborate with architects and software teams to define and implement SDMA micro-architecture, RTL, and firmware, focusing on delivering high-quality, low-power design solutions.

Experience Level

Level - Mid-Career

Responsibilities

• Drive RTL and firmware design and synthesis for selected system IP components.
• Deliver high-performance, low-power design implementations.
• Execute front-end integration flows (synthesis, LINT, DFT, etc.) and generate high-quality netlists.
• Collaborate with RTL owners and physical design teams to achieve timing closure and validate reports.
• Contribute to RTL development of system IP blocks: study specifications, implement functionality, and work closely with verification engineers on debug and issue resolution.

Requirements

• Hands-on experience with synthesis, timing analysis, and formal verification.
• Strong background in ASIC or FPGA projects.
• Proficiency in Verilog design.
• Familiarity with front-end EDA tools and flows.
• Advanced scripting/programming skills in Ruby, Perl, Python, and Makefile.
• Proven debugging skills in pre-silicon simulation/emulation and post-silicon validation at RTL and system levels.
• Firmware development experience (highly desirable).

Education Requirements

MMasters or Bachelors in Electrical Engineering or similar is preferred.