RTL Design Engineer

Role Summary

This position is for an RTL Design Engineer within the Security IP (SECIP) team at Advanced Micro Devices. The team specializes in designing and verifying embedded microprocessor subsystems and hardware accelerators that boost performance and functionality for System-on-Chip (SoC) products. The primary focus is on enhancing features such as security policy management and cryptography.

Experience Level

This role is aimed at candidates with substantial experience in hardware RTL design and verified block-level design. An emphasis is placed on an ability to troubleshoot and collaborate effectively in a dynamic team environment.

Responsibilities

• Develop and maintain block level RTL IP and microprocessor subsystems’ specifications and methodologies.
• Debug and develop RTL designs, integrating them with existing verification frameworks.
• Triage regressions and resolve technical issues impacting design closures.
• Engage in the formulation and refinement of verification test plans.
• Address integration issues with teams responsible for Silicon validation.
• Contribute technical leadership on design methodology and advanced problem resolution.

Requirements

Applying candidates must possess a rich understanding of CPU and MP subsystem architectures, along with familiarity in FPGA simulation methodology. Candidates should be skilled in Verilog and System Verilog, alongside competency in scripting languages such as Tcl, Ruby, and Python. A solid grasp of RTL design practices and ASIC design tools is also required.

Education Requirements

A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is necessary for this role.