RTL Design Engineer

Job Title

RTL Design Engineer

Role Summary

The AMD IOHUB Team is seeking an ASIC Design Engineer to focus on I/O connectivity and virtualization technologies. This role involves participation in all aspects of IP design, including architecture, requirements, and execution. You will play a crucial role in delivering quality technologies to market.

Experience Level

Level - Mid-Career

Responsibilities

You will be responsible for:

• Understanding the functional and performance requirements of the IOHUB within various SOCs.
• Driving IP/SOC design infra decisions to ensure optimal consumption within the SOC context.
• Guiding and acting as a liaison between IP and SOC design teams regarding synthesis and physical layout issues.
• Scoping requirements and resources to meet project schedules.
• Providing hands-on leadership of a small team of Engineers as needed.
• Signing off on IP quality for SOC delivery.
• Communicating effectively with multi-disciplined global teams.
• Gathering and presenting technical updates in status meetings.

Requirements

Candidates must meet the following qualifications:

• Proven ASIC design experience, specifically in RTL design on large ASIC projects.
• A strong background with industry-standard synthesis tools and back-end timing closure.
• Proficient in Verilog and System Verilog.
• Excellent analytical skills, attention to detail, and written communication capabilities.
• Understanding of IP integration and SOC interactions.
• Ability to work independently and demonstrate reliable problem-solving skills.
• Team player with leadership abilities.

Education Requirements

Bachelor of Science degree in Electrical Engineering, Computer Science, or Computer Engineering.