RTL Design Engineer

Role Summary

As a member of the Infinity Fabric Architecture and RTL team, you will help build the next generation coherent interconnect to provide connectivity between CPU, GPU, and special purpose accelerators. This role involves working on custom-designed Infinity Data Fabric, addressing various markets, including traditional servers, high performance computing, client desktop and laptop PCs, machine intelligence, graphics, console gaming, embedded, and customer-specific applications.

Experience Level

Level - Mid-Career

Responsibilities

• Early architectural/performance exploration through micro architectural definition and design.
• Optimize the design to meet power, performance, area, and timing requirements.
• Write easily readable and synthesizable Verilog RTL.
• Run unit level testing to ensure quality code delivery to the Design Verification Team.
• Create assertions for coverage and analyze design coverage.
• Produce well-written block level design documentation.
• Participate in post-silicon functional and performance debug and tuning.

Requirements

• Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs.
• Excellent knowledge of Verilog and System Verilog.
• Working knowledge of C, C++, and a scripting language like Perl or Python.
• Strong understanding of digital electronics and high-speed designs (>1GHz).
• Good understanding of multi-processor coherency, memory ordering, I/O ordering, interrupts, MMU, and caches.
• Good debugging and analytical skills.
• Exposure to Design for Test and understanding of scan concepts and writing DFT friendly RTL.
• Working knowledge of x86 or ARM ISA is a plus.

Education Requirements

BS, MS, or PhD degree in Electrical or Computer engineering preferred.