RTL Design and Verification Engineer (R&D Engineering) Sr. Engineer

Role Summary

This position involves designing and verifying RTL for advanced Silicon Lifecycle Management (SLM) IPs, focusing on next-generation 3D-IC projects.

Experience Level

2+ years of hands-on experience in RTL design and verification.

Responsibilities

• Designing and verifying RTL for SLM IPs.
• Developing comprehensive test cases to ensure functionality and performance.
• Collaborating with teams to resolve technical issues, including debugging and analysis.
• Staying updated with trends in SLM and 3D-IC technologies.
• Contributing to the improvement of verification methodologies.
• Documenting design specifications and verification results.
• Participating in code reviews and technical discussions.

Requirements

Proficiency in EDA tools, Verilog, System Verilog, and TCL scripting is required, along with experience in Unix/Linux. Excellent communication skills in English and debugging capabilities are essential.

Education Requirements

BS/MS in Computer Science, Electrical Engineering, or a related field is required.