R&D Engineering Sr. Staff Engineer

Role Summary

This role involves optimizing performance in Verilog/SystemVerilog simulation through expert-level C++ programming and exploring GPU acceleration techniques. The goal is to enhance simulation reliability and speed for semiconductor companies.

Experience Level

Senior, with 8-10 years of relevant experience expected.

Responsibilities

The position includes:

• Architecting and optimizing simulation engine kernels for VCS RTL simulator using advanced C++ techniques.
• Implementing GPU or other acceleration strategies to reduce simulation runtimes.
• Ensuring accurate simulation through deep knowledge of Verilog/SystemVerilog LRM.
• Integrating AI-powered tools to automate code generation and debugging.
• Mentoring junior engineers and fostering technical growth.
• Collaborating with distributed R&D teams to drive innovation.
• Analyzing performance bottlenecks and proposing improvements for verification strategies.

Requirements

Applicants must have:

• Expert-level proficiency in C++ with experience in performance-critical software development.
• Deep understanding of Verilog/SystemVerilog Language Reference Manuals (LRM).
• Experience with GPU/CUDA programming or other hardware accelerators.
• Familiarity with AI-powered development tools like Cursor and GitHub Copilot.
• Strong architectural design skills and experience in mentoring junior engineers.

Education Requirements

Not specified.

About the Company

Company: Synopsys

Headquarters: Mountain View, California, USA

Synopsys is a leading company in electronic design automation (EDA) and semiconductor IP solutions. It provides tools and services for designing and verifying complex semiconductor devices and systems. The company plays a pivotal role in the semiconductor industry, helping engineers innovate and deliver higher-quality products faster. Synopsys is committed to advancing technology standards and offers a range of software and hardware solutions to its clients globally.