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Principal Interconnect Micro-architect and RTL Design Engineer

Advanced Micro Devices
Full-time
Remote friendly (Santa Clara, California, United States)
Worldwide
Level - Mid-Career

Company Overview

Advanced Micro Devices, Inc. (AMD) is a prominent player in the semiconductor industry, focused on developing high performance computing solutions including processors for data centers, personal computers, and embedded systems.

Role Summary

The Principal Interconnect Micro-architect and RTL Design Engineer will lead efforts in achieving optimal Power, Performance, and Area (PPA) for SoC coherent Interconnects Data Fabrics IPs in next-generation AMD AI devices. The role requires collaboration with multiple teams, ensuring the design and microarchitecture meet the required standards for high-performance SoCs.

Experience Level

This is a mid-career level position requiring substantial experience in microarchitecture design and digital IP development.

Responsibilities

  • Lead technical microarchitecture efforts focusing on scalability and modularity within the AMD Data Fabric RTL design team.
  • Identify and drive initiatives for enhanced switch fabric scalability across Data Center AI accelerator SoCs.
  • Develop relationships with a broader design community to ensure alignment on architecture and technical needs.
  • Monitor trends in switch fabric hardware architecture and drive technical specifications for Data Fabric IP.
  • Collaborate cross-functionally to assess technical challenges and propose microarchitecture solutions.
  • Contribute to knowledge sharing and optimization in Data Fabric architecture and design.
  • Coordinate closely with various design teams on area refinements, timing targets, and verification processes.
  • Assist Post-Si teams in debugging performance and functional issues.

Requirements

  • Proven experience in scalable, configurable switch fabric designs
  • Experience in modern heterogeneous systems (CPU, GPU, and AI accelerators)
  • Automation skills in SOC and IP creation for various microarchitectures
  • Strong background in RTL design with Verilog and SystemVerilog expertise
  • Familiarity with front-end tools related to synthesis and verification
  • Strong scripting skills (e.g., Perl, Python, Unix Shell)
  • Excellent interpersonal and communication skills, with leadership experience in a collaborative environment

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is preferred.