Principal Engineer - PCIe RTL Design

Job Title

Principal Engineer - PCIe RTL Design

Role Summary

The Principal Engineer will lead micro-architecture definition, RTL implementation, integration, and delivery of PCIe/CXL subsystems within Marvell's Data Centre Engineering (Compute & Storage) organization. This role partners with architecture, verification, physical design, DFT, firmware, and validation teams to deliver production-quality silicon subsystems.

Position includes technical leadership, design quality improvements, and mentoring of junior designers in PCIe/CXL RTL design and subsystem integration.

Experience Level

Senior — requires extensive senior-level experience; the posting indicates 18+ years of relevant RTL design experience.

Responsibilities

Primary responsibilities include ownership of PCIe/CXL subsystem design through implementation and silicon bring-up. Key activities:

• Define PCIe/CXL subsystem micro-architecture and drive RTL implementation and integration.
• Translate architecture requirements into robust RTL designs in collaboration with architecture teams.
• Work with design verification teams on test-plan reviews, debug, and coverage closure.
• Collaborate with physical design and DFT teams to ensure PD-friendly and DFT-ready RTL.
• Support silicon bring-up and post-silicon debug with firmware and validation teams.
• Drive coding best practices, design quality improvements, and reuse across projects.
• Participate in design and milestone reviews and cross-functional technical discussions.
• Mentor junior designers and provide technical leadership within the PCIe/CXL domain.

Requirements

Must-have technical skills and experience (summary):

• Proven delivery of complex PCIe/CXL IP or subsystems from architecture through RTL closure (end-to-end RTL design and sign-off).
• Strong hands-on SystemVerilog / Verilog RTL development skills.
• Deep understanding of PCIe protocol architecture (link, transaction, PHY interactions) and CXL.io, CXL.cache, CXL.mem semantics.
• Experience with ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE).
• Design experience for high-performance, low-latency data paths, ordering, coherency, and error handling.
• Knowledge of clocking, resets, CDC/RDC, low-power techniques, and performance optimization.
• Experience supporting lint, CDC/RDC analysis, synthesis flows, and design sign-off.
• Proficient in subsystem/SoC-level functional and performance debug.
• Familiarity with industry EDA tools (Synopsys, Cadence, Mentor/Siemens).
• Scripting proficiency (Tcl, Perl, Python) and experience with version control systems (GIT, SVN).

Nice-to-have:

• Prior experience with silicon bring-up and post-silicon validation on PCIe/CXL subsystems.

Education Requirements

Bachelor's or Master's degree in Electronics / Electrical Engineering is specified in the posting. The role also indicates 18+ years of relevant RTL design experience.

About the Company

Company: Marvell Technology

Headquarters: Santa Clara, California, United States

Marvell’s semiconductor solutions serve as essential building blocks of the data infrastructure connecting our world, driving innovation across enterprise, cloud, AI, and carrier architectures. The company focuses on creating transformative technology that shapes the future.