Principal Design Engineer

Job Title

Principal Design Engineer

Role Summary

Senior functional verification engineer for the DDR Subsystem Verification team based in Bangalore. The role focuses on verifying DDR memory controller and PHY IP, maintaining and extending the verification environment, delivering reference demosim testbenches, ensuring functional and code coverage, and supporting customer integration.

The engineer will lead verification activities, represent the verification team in technical discussions, review deliverables, track progress and risks, and mentor team members.

Experience Level

Senior — 8+ years of design verification experience; strong expertise in SystemVerilog and UVM and familiarity with DDR family memory protocols (DDR, LPDDR, HBM).

Responsibilities

Primary responsibilities include:

• Perform functional verification of DDR subsystem (memory controller and PHY IP).
• Develop, extend and maintain the verification environment and testbenches (including demosim reference test patterns).
• Create test plans, run regression suites, and ensure customer configurations are validated.
• Ensure achievement of functional and code coverage goals and track verification metrics.
• Debug RTL and verification failures; provide self-sufficient RTL/verification debugging.
• Represent the verification team in internal and external technical discussions and customer interactions.
• Review technical deliverables, guide team members, and mentor engineers.
• Track verification progress, identify risks, and define mitigation plans.
• Contribute to verification process and methodology improvements.

Requirements

Must-have:

• 8+ years of design verification experience with SystemVerilog and UVM.
• Strong fundamentals in functional verification, environment planning, and test plan generation.
• Hands-on experience developing verification environments and writing UVM/SystemVerilog.
• Prior RTL design experience in Verilog to enable effective debugging.
• Experience verifying complex designs and leading projects to verification closure.
• Knowledge of verification components, metrics, and coverage-driven verification.
• Strong written, verbal, presentation, and interpersonal skills.

Nice-to-have:

• Prior IP verification experience for memory IP (DDR, HBM, LPDDR).
• Experience with PHY IP verification or related memory protocols.

Education Requirements

BE/BTech/ME/MTech in Electrical, Electronics, VLSI or related fields as specified in the source posting.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.