Physical Design Graduate Intern

Role Summary

Join Altera as a Physical Design Intern, contributing to the implementation of Altera IPs such as PCIe, Ethernet, CXL, and DR. This internship involves collaboration with both local and remote teams within the physical design flow.

Experience Level

Student / Intern, pursuing a Master's degree or PhD in computer engineering, electrical engineering, engineering science, computer science, mathematics, or a related field.

Responsibilities

Key responsibilities include:

• Assisting with various aspects of the physical design flow: synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
• Utilizing scripting to run regressions and automate workflows.
• Analyzing logs and reports to debug issues and recommend solutions.
• Engaging with teams both locally and remotely.

Requirements

To qualify, you should have:

• Pursuing a University Degree (e.g., EE, CE, CS, or related fields).
• Digital design skills (FPGA or ASIC) using Verilog/VHDL/System Verilog.
• Scripting knowledge (e.g., Python, Tcl).
• A strong desire to learn and be a self-starter.
• Excellent communication skills and a team-oriented mindset.

Education Requirements

Must be pursuing a Master's degree or PhD in relevant fields such as computer engineering, electrical engineering, or computer science.

About the Company

Company: Altera

Headquarters: Bengaluru, Karnataka, India

Altera provides leadership programmable solutions for applications ranging from cloud to edge, unveiling limitless AI possibilities. Their extensive product portfolio includes FPGAs, CPLDs, Intellectual Property, development tools, and System on Modules aimed at accelerating innovation in various fields.