The Physical Design Engineer Intern will contribute to the physical implementation of silicon designs. The focus will be on ensuring the design readiness for manufacturing. Interns will engage in various aspects of the physical design flow including synthesis, place and route, timing analysis, clocking, and integration.
This position is intended for candidates currently pursuing a relevant degree with a foundational understanding of physical design processes. Candidates should demonstrate knowledge in RTL design and ASIC verification.
Candidates must be pursuing a Master’s degree (MTech, ME) with exposure to RTL design using Verilog and familiarity with ASIC verification tools and Perl.
Candidates should be currently enrolled in a graduate program relevant to the field and have completed coursework in digital design and ASIC methodologies.