PE Layout Design

Role Summary

This position is for a PE Layout Design engineer at Rambus in Bangalore, primarily focused on developing advanced memory interface chips and ensuring the quality and performance of layout deliverables.

Experience Level

The role requires extensive experience, with candidates expected to have between 12 to 15 years in relevant design and engineering disciplines, particularly in semiconductor layout.

Responsibilities

• Lead layout team and manage layout deliverables for assigned projects.
• Utilize Cadence Virtuoso XL/VXL for layout design and ensure compliance through LVS, DRC, Antenna, and Density checks using Calibre.
• Collaborate with global cross-functional teams to resolve layout issues.
• Conduct reviews for floorplan, powergrid, and signal planning.
• Handle bump-out planning and die area estimation.
• Address reliability issues such as EMIR, EOS, ESD, and latch-up.
• Implement standard layout practices, focusing on noise isolation, layout matching, and parasitic considerations.

Requirements

Candidates must possess a degree in Electrical or Electronic Engineering or a related field. They should have substantial experience with layout design in various technology nodes like 22nm, 16nm, 12nm, and 7nm, as well as a solid understanding of semiconductor physics and layout-dependent effects. Scripting skills in skill/Perl/TCL are a plus. Candidates should be self-motivated, team-oriented, and adept at problem-solving.

Education Requirements

Degree in Electrical/Electronic Engineering or equivalent mandatory.