PCIe Verification Design Engineer

Role Overview

The PCIe Verification Design Engineer will focus on planning, building, and executing the verification and validation of features for AMD's programmable devices. The role emphasizes PCIe/CXL, DMA, and associated solution IPs, aiming to ensure the highest reliability and performance in cutting-edge technology.

Experience Level

This position requires a mid-career level of experience, with candidates expected to have a strong foundation in digital design and verification.

Key Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to verify new features.
• Architect moderate-complexity RTL designs for integration into larger SoCs.
• Create test plan documentation that considers interactions among features, hardware, firmware, and software drivers.
• Estimate time requirements for new feature tests and modifications to the test environment.
• Develop directed and random verification tests using class-based techniques, preferably UVM.
• Debug failures in simulations, labs, or production, working with engineers to resolve defects.
• Review functional and code coverage metrics and update tests accordingly.

Candidate Requirements

The ideal candidate will possess a deep passion for System on Chip (SoC) architecture, digital design, verification, and validation. Strong communication skills and experience collaborating with remote teams are essential. Candidates should exhibit strong analytical and problem-solving abilities.

Education Requirements

Applicants must hold a Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering.