PCIe Subsystem Verification Engineer

Role Summary

The Solutions Engineering team at Arm seeks an experienced PCIe and CXL expert for verifying functionality at the sub-system level for High-Speed IOs. Join a diverse team of Architects, RTL design, and verification engineers across multiple locations, including the UK, US, Canada, and India, focusing on next-generation SoCs.

Experience Level

5+ years of experience in the design or verification of sophisticated PCIe or CXL subsystems or SoCs, ideally with a Bachelor's or Master's degree in Computer Science or Electrical/Computer Engineering.

Responsibilities

• Conduct verification of Sub-System integration, IO scenario verification, and interoperability testing with Arm and third-party IPs.
• Review architecture and design specifications to develop a functional verification strategy.
• Craft test plans and develop SystemVerilog/Verilog/UVM testbenches and tests.
• Debug test failures and issues effectively.
• Enhance verification methodologies used by the team and collaborate on design microarchitecture and system performance.
• Assist with project management activities and support junior team members.

Requirements

• Solid understanding of digital hardware design and Verilog HDL.
• Experience in PCIe and CXL feature verification.
• Familiarity with PCIe & CXL IPs and simulation/emulation platforms.
• Skilled in debugging and UVM based verification methodologies.
• Knowledge of verification strategies and test plan creation.
• Understanding of formal verification methodologies is beneficial.

Education Requirements

Bachelor's or Master's degree in Computer Science or Electrical/Computer Engineering (or a related field).