MTS Silicon Design Engineer

Role Summary

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.

Experience Level

Preferred experience includes proficiency in IP level ASIC verification, debugging firmware and RTL code, and using UVM testbenches in Linux and Windows environments.

Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, hardware, firmware, and software driver use cases.
• Estimate the time required to write new feature tests and required changes to the test environment.
• Build directed and random verification tests.
• Debug test failures to determine root causes; work with RTL and firmware engineers to resolve design defects and correct test issues.
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet coverage requirements.

Requirements

• Proficient in using UVM testbenches and working in Linux and Windows environments.
• Experienced with Verilog, System Verilog, C, and C++.
• Strong background in C++, good understanding of UVM concepts and SystemVerilog language.
• Scripting knowledge in Perl, Ruby, Makefile, shell preferred.
• Exposure to leadership or mentorship is an asset.
• Prior exposure to video codec systems or multimedia solutions is desirable.

Education Requirements

Bachelors or Masters degree in computer engineering or Electrical Engineering.