Mixed Signal AMS Co-Simulation Verification Engineer

Role Summary

We are a leader in EDA tools, semiconductor IP, and silicon engineering solutions, dedicated to driving innovation in various applications, from AI to automotive technologies.

Experience Level

This position is suitable for both new graduates and experienced engineers, with mentoring opportunities available for more seasoned candidates.

Responsibilities

• Define, implement, and track comprehensive verification test plans to ensure robust coverage and quality for SERDES IP.
• Build, enhance, and maintain top-level UVM-based System Verilog testbenches and AMS co-simulation environments, integrating RTL, behavioral models, and transistor-level netlists.
• Perform functional verification of SERDES blocks, including TX/RX data paths, equalization algorithms, adaptation loops, CDR behavior, PLL locking, and analog/digital interactions.
• Debug and resolve simulation failures across analog, digital, and mixed-signal domains.
• Conduct design reliability checks such as electromigration (EM) and IR analysis to ensure silicon robustness.
• Collaborate with mixed-signal designers and system architects globally.

Requirements

• Bachelor’s or master’s degree in electrical engineering or a related field.
• Strong foundational understanding of analog circuits like op-amps, PLLs, and ADCs.
• Exposure to Verilog/System Verilog and AMS concepts or circuit design.
• Experience with AMS tools such as HSPICE, Custom Sim, and scripting languages like Python.
• Ability to debug analog-digital interactions and define robust verification strategies.

Education Requirements

Bachelor’s or master’s degree in electrical engineering or a related field is required, with preference given to candidates with a master’s degree, especially for new graduates.