Memory Subsystem Verification Engineer

Role Overview

The Memory Subsystem team is currently seeking a Verification Engineer who will be instrumental in the design and verification processes for high-speed memory subsystem solutions, including LPDDR and DDR technologies. This position involves utilizing advanced verification techniques, particularly the Universal Verification Methodology (UVM), while participating in both hardware and firmware co-verification.

Experience Level

This role is targeted towards professionals with experience in verification engineering who possess strong collaboration and problem-solving skills. Candidates should be detail-oriented and able to communicate effectively within a team dynamic.

Key Responsibilities

• Develop and maintain verification environments using UVM for memory subsystems.
• Create, execute, and manage test plans and test cases.
• Engage in co-verification of firmware and hardware components.
• Integrate and debug Memory Verification IP, monitors, and transactors.
• Analyze coverage metrics and work to resolve coverage deficiencies.
• Investigate simulation failures and collaborate with various teams to find solutions.

Essential Qualifications

Candidates must have a solid foundational knowledge of Object-Oriented Programming and proficiency in System Verilog, UVM, and C/C++. Experience in digital design verification or relevant coursework is required.

Education Requirements

A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is necessary for this position.