Memory Subsystem Verification Engineer

Role Overview

The Memory Subsystem Verification Engineer will be responsible for the design, development, and verification of high-speed LPDDR/DDR memory subsystem solutions at AMD. This position requires hands-on experience with IP- and subsystem-level verification, engaging in pre-silicon firmware and hardware co-verification utilizing hybrid simulation environments and the Universal Verification Methodology (UVM).

Experience Level

We are seeking a detail-oriented verification professional who values collaboration and is interested in innovative memory subsystem technologies.

Key Responsibilities

• Develop and maintain UVM-based verification environments for memory subsystems and associated IP.
• Create and execute comprehensive test plans, test cases, and regression tests.
• Engage in firmware and hardware co-verification activities.
• Integrate and debug Memory VIP, transactors, monitors, and checkers.
• Analyze functional and code coverage and assist in addressing coverage gaps.
• Debug simulation failures in collaboration with cross-functional teams.

Qualifications

The ideal applicant should possess a strong foundational understanding of Object-Oriented Programming, along with significant knowledge of verification tools and methodologies.

Education Requirements

A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline is required.