Memory Subsystem Enablement Verification Engineer

Role Overview

The Memory Subsystem Enablement Verification Engineer will focus on pre-silicon verification of high-speed memory technologies such as LPDDRx and DDRx. The successful candidate will engage in hybrid co-simulation environments to ensure product readiness, contributing to the definition, design, and development of industry-leading memory subsystem solutions.

Experience Level

We are seeking a candidate with a strong background in engineering, specifically those who have significant experience in verification processes within the semiconductor industry.

Key Responsibilities

• Utilize expertise in C, C++, and System Verilog to support the development and verification of memory subsystems.
• Develop advanced testbench architectures and conduct verification of both IP and subsystem levels.
• Implement and maintain co-verification environments while debugging production-level firmware.
• Create comprehensive test plans, evaluating code and functional coverage to enhance verification processes.
• Collaborate with cross-functional teams to adapt to new toolsets and maintain test suite effectiveness.

Required Qualifications

• Bachelor’s degree in Electrical or Computer Engineering with relevant experience; a Master's or PhD is preferred.
• Proficiency in C, C++, System Verilog, and experience in co-verification of hardware and firmware.
• Familiar with DDR/JEDEC standards, UVM object-oriented design, and architectural modeling.
• Strong interpersonal skills and the ability to work collaboratively with teams across the organization.

Education Requirements

Bachelor’s degree in Electrical or Computer Engineering, or a Master's/PhD in a relevant field, combined with significant industry experience.