Memory Subsystem Enablement Verification Engineer

Job Title

Memory Subsystem Enablement Verification Engineer

Role Summary

The Memory Subsystem team is seeking experienced pre-silicon Verification engineers responsible for ensuring the readiness of high-speed LPDDRx, DDRx, and associated IPs through advanced co-simulation hybrid environments. This role involves active participation in the definition, design, and development of industry-leading memory subsystem solutions.

Experience Level

Level - Mid-Career

Responsibilities

• Proficiency in C, C++, System Verilog.
• Ground-up development and verification of IP and Subsystem.
• Advanced testbench architecture and microarchitecture development, including co-verification.
• In-depth knowledge of code and functional coverage and test plan relationships.
• Development and troubleshooting of co-verification environments.
• Maintain test suite through firmware modifications and custom stimulus development.
• Develop subsystem and block level test plans.
• Ability to learn and adapt to new tools and frameworks.

Requirements

• Education Requirements
• Bachelor’s degree in electrical or computer engineering with relevant experience, or a Master's or PhD in Electrical or Computer Engineering.