Memory Subsystem Design Verification Engineer

Role Summary

The Memory Subsystem Design Verification Engineer position involves the verification of high-speed LPDDR/DDR memory subsystems and associated intellectual property (IP). This includes pre-silicon verification and the development of solutions using Universal Verification Methodology (UVM) in a hybrid co-simulation environment.

Experience Level

This position is suitable for mid-career professionals with a solid background in verification engineering, specifically in FPGA validation and memory subsystem designs.

Responsibilities

Key responsibilities include designing and implementing advanced verification environments using System Verilog and UVM methodologies. This encompasses maintaining test benches, managing regressions, analyzing coverage metrics, and collaborating with cross-functional teams to ensure comprehensive verification solutions are delivered. Specific duties include:

• Verification of IP and subsystems using UVM and System Verilog
• Integration and debugging of Memory VIP
• Developing transactor-based stimulus and maintaining test suites
• Evaluating new toolsets and frameworks for verification improvement

Requirements

Candidates must demonstrate proficiency in C/C++, System Verilog, and scripting languages such as Python and shell. A background in testbench architecture and knowledge of code coverage is expected. Successful applicants should also possess the ability to design and debug co-verification environments and be adaptable to new methodologies.

Education Requirements

A Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is required. Practical experience in verification engineering will be considered equivalent.