Memory Subsystem Design Verification Engineer

Role Summary

The Memory Subsystem team seeks a Verification Engineer to work on the design and development of high-speed LPDDR/DDR memory subsystem solutions. This position focuses on pre-silicon firmware co-verification and involves using hybrid co-simulation environments along with Universal Verification Methodology (UVM).

Experience Level

The role is suitable for individuals with a strong background in verification engineering, particularly those proficient in advanced verification techniques and methodologies.

Responsibilities

• Design and implement advanced verification environments for memory subsystems and associated intellectual property (IP) using System Verilog and UVM.
• Develop and maintain test benches, co-verification frameworks, and test suites aligned with firmware features.
• Integrate and debug Memory VIP while collaborating with cross-functional teams to ensure effective verification solutions.
• Analyze coverage metrics and manage regression tests to enhance verification processes.
• Adapt to new tools and frameworks, contributing to improvements and documentation of results.

Requirements

• Proficient in C/C++, System Verilog, UVM, and scripting languages such as Python.
• Experience in IP and subsystem verification using System Verilog/UVM and VCS.
• Strong background in testbench architecture and firmware co-verification.
• Ability to design and debug production-level firmware co-verification environments.
• Knowledge in managing code and functional coverage.

Education Requirements

Bachelor's or master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience in verification engineering.