Memory Subsystem Design and Integration Engineer

Role Summary

The Memory Subsystem team at AMD is seeking a RTL and Integration Engineer to design and develop high-speed LPDDR/DDR memory subsystem solutions. This role will involve the complete subsystem integration and collaboration with various teams across different locations.

Experience Level

This position is targeted at candidates with a strong technical background in RTL and integration engineering, emphasizing a system-level mindset and the ability to complete assigned tasks independently.

Responsibilities

• Design, develop, and maintain RTL for memory subsystem IP and integration logic using Verilog/System Verilog.
• Participate in architecture and micro-architecture definition and translate requirements into RTL.
• Integrate IP blocks to create complete DDR/LPDDR memory subsystems.
• Collaborate with verification teams on test plans, debug issues, and resolve pre-silicon problems.
• Work with physical design teams on timing targets, floor planning, and CDC strategies.
• Analyze and debug complex functional, timing, and integration issues.
• Develop and maintain subsystem documentation and timing diagrams.
• Support activities for pre-silicon and post-silicon bring-up.

Requirements

The ideal candidate should have substantial experience in DDR/JEDEC standard IP, memory controllers, and related subsystems. Proficiency in Verilog and System Verilog is essential, along with a strong foundational knowledge of Object-Oriented Programming concepts.

Education Requirements

A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field is required.