Memory Subsystem Design and Integration Engineer

Role Summary

The Memory Subsystem team at Advanced Micro Devices is seeking an RTL and Integration Engineer. This position involves the design, development, and integration of high-speed LPDDR/DDR memory subsystem solutions and associated IP.

Experience Level

The ideal candidate should possess a strong technical background in RTL design and system integration, with the ability to work independently across multiple teams.

Responsibilities

The key responsibilities of this position include:

• Designing, developing, and maintaining RTL for memory subsystem IP and integration logic using Verilog/System Verilog.
• Participating in architecture and micro-architecture definition.
• Integrating IP blocks to create complete DDR/LPDDR memory subsystems.
• Collaborating with verification teams on test plans and debugging.
• Working with physical design teams on timing targets and floor planning.
• Analyzing and debugging complex integration issues.
• Maintaining subsystem documentation and timing diagrams.
• Supporting pre-silicon and post-silicon bring-up activities.

Requirements

The following qualifications are required:

• Strong proficiency in Verilog and System Verilog.
• Experience with DDR/JEDEC standard IP, DDR PHY, memory controllers, or memory subsystems.
• Ability to debug RTL and integration issues.
• Knowledge of SVA/OVL and synthesizable assertions.
• Experience in complex SoC environments.
• Familiarity with simulation tools and version control systems (Git/Perforce).