Memory PHY RTL Design Engineer

Role Summary

The Memory PHY team at Advanced Micro Devices is seeking an experienced Design Engineer specialized in RTL and Firmware development for high-speed LPDDR and DDR IPs. The role involves engaging in the design and development phases of cutting-edge Memory PHYs and interface IP, focusing on innovation and enhancing existing methodologies.

Experience Level

This position is suitable for professionals with a background in digital design engineering and relevant experience in RTL implementation.

Responsibilities

The primary responsibilities of the Memory PHY RTL Design Engineer include:

• Microarchitectural design and RTL implementation of IP features.
• Synthesis, static timing analysis, CDC/RDC, UPF Design/Simulation, power optimization, and gate simulation.
• Development of PHY Digital Architecture from initial pathfinding, coding, to verification and physical implementation.
• Collaboration with firmware teams to design firmware sequences and algorithms.
• RTL design analysis for power and timing optimization.
• Working with the design verification team to ensure accurate execution of design features.
• Participating in design specifications and RTL code reviews.

Requirements

Candidates should possess a strong expertise in digital design, specifically:

• Proficiency in Verilog, System Verilog, C, and a scripting language (Python, Perl, TCL preferred).
• Experience in debugging firmware and RTL code using simulation tools.
• Familiarity with UVM testbenches and Linux/Windows environments.
• Understanding of clocking architectures and CDC methodology.
• Experience with SERDES, DDR, Memory Controller, or MAC design.
• A strong grasp of computer organization and architecture principles.
• Mixed signal RTL experience and leadership exposure are pluses.

Education Requirements

A Bachelor's or Master's degree in Computer Engineering or Electrical Engineering is required.