Memory Mask Design Engineer

Role Overview

The Memory Mask Design Engineer position at NVIDIA requires a professional committed to the design and implementation of innovative high-performance CMOS integrated circuits. The job involves handling high-speed digital memory circuit designs in compliance with advanced foundry process nodes.

Experience Level

This role is aimed at candidates with at least 2 years of relevant experience in advanced CMOS process design.

Responsibilities

The key responsibilities include:

• Implementing IC layout for high-performance CMOS integrated circuits in 3nm, 5nm, and 7nm nodes.
• Delivering layouts for the Full Custom Memory group specializing in digital memory circuits.
• Adopting best practices for composing digital memory layouts.
• Following established company procedures for all IC layout activities.

Requirements

To be successful in this role, candidates must have:

• B.E/B Tech / M Tech in Electronics or equivalent.
• A minimum of 2 years of proven experience in memory layout in advanced CMOS processes.
• Expertise with industry-standard EDA tools, specifically Cadence.
• Experience with high-performance memory layouts.
• Strong understanding of layout principles and top-level verification processes.

Education Requirements

A bachelor's or master's degree in Electronics or a related field is required.