Logic Design Intern FPGA Design Verification Intern - Summer 2026

Role Summary

As an intern, you will work alongside experienced design and verification engineers to help design, verify, and validate cutting‑edge FPGA‑based solutions that power our next‑generation instruments. This internship offers hands‑on exposure to real engineering challenges, modern verification methodologies, and industry‑standard tools.

Experience Level

Entry level, suitable for students currently enrolled in a degree program.

Responsibilities

• Assist in the design, verification, and validation of FPGA-based solutions.
• Engage with current engineers to understand modern verification methodologies.
• Work on real engineering challenges and learn to utilize industry-standard tools.

Requirements

• Currently enrolled in a BS or MS degree program in Electrical Engineering or Computer Engineering.
• BS students must have Junior or Senior standing with a minimum GPA of 3.2.
• MS students must maintain a minimum GPA of 3.2.
• Coursework must include FPGA design and verification using Verilog, SystemVerilog, or another HDL.
• Excellent written and verbal communication skills.
• Ability to thrive in a fast-paced engineering environment.
• Strong self‑starter mindset with proactive problem-solving abilities.
• Must be available to work on-site at the North Reading, Massachusetts office.
• Availability for work during the summer break (May–September 2026), based on school schedule.
• Local candidates only; no relocation provided and not eligible for visa sponsorship.

Education Requirements

Enrolled in a BS or MS degree program in Electrical Engineering or Computer Engineering.