This position involves developing logic designs, register transfer level (RTL) coding, and simulations for IPs utilized in Server products. The engineer will participate in defining architecture and microarchitecture features while ensuring that designs meet power, performance, area, and timing goals.
Applicants should have significant experience, typically requiring around 6 years in the industry with a focus on IPs that have been successfully produced and taped out.
Minimum qualifications include a B.Tech/M.Tech degree, experience in digital design methodology, and a strong understanding of Verilog/System Verilog. Hands-on familiarity with emulation, silicon bring-up, and debugging is essential.
A degree in Electrical Engineering, Computer Engineering, or a related field is required.