Lead Design Engineer

Role Overview

The role of a Lead Design Engineer at Cadence involves taking charge of design verification projects, especially for complex semiconductor designs. This position requires hands-on expertise in System Verilog and UVM coding for the development of functional verification environments.

Experience Level

The ideal candidate should possess at least 4 years of experience in Design Verification, particularly with a strong foundation in functional verification fundamentals.

Key Responsibilities

The Lead Design Engineer will be responsible for:

• Leading design verification projects from conception through to closure.
• Creating and executing test plans.
• Developing and planning verification environments, specifically using System Verilog and UVM.
• Collaborating with team members to enhance verification methodologies and processes.
• Prioritizing tasks and mentoring junior engineers.

Job Requirements

To qualify for this position, candidates must meet the following requirements:

• B.E/B.Tech/M.E/M.Tech in Electrical, Electronics, or VLSI engineering.
• Strong hands-on experience with System Verilog and UVM.
• Extensive knowledge of design verification processes and methodologies.
• Familiarity with memory IP verification (DDR/HBM/GDDR) is a plus.

Education Requirements

A degree in Electrical, Electronics, or VLSI engineering is required to apply for this position.