Lead Design Engineer

Job Title

Lead Design Engineer

Role Summary

Lead development and delivery of DDR/HBM memory PHY/Controller IP as part of the digital IP design team. The role combines hands-on design, verification, and technical leadership to deliver protocol-compliant silicon-ready IP.

Work with cross-functional teams to implement logic, run simulations, and drive multiple IC design projects to completion.

Experience Level

Senior — typically 7+ years of experience in digital IC development projects; demonstrated ability to lead and contribute to complex chip-design efforts.

Responsibilities

Primary responsibilities include design, verification, and delivery of DDR/HBM IP and related digital blocks.

• Design and simulate logic for memory PHY/Controller IP and related digital subsystems.
• Develop and maintain Verilog RTL and testbenches; run and analyze simulation flows.
• Ensure compliance with JEDEC-DDR/HBM, DFI and AMBA protocols; implement protocol features and interoperability.
• Drive verification, debug silicon issues, and support bring-up activities.
• Act as technical lead or senior contributor across multiple design projects; coordinate with system, firmware, layout, and verification teams.
• Communicate design status, risks, and trade-offs clearly to stakeholders.

Requirements

Key qualifications and skills required for successful performance in this role.

• Must-have: At least seven years of experience on digital IC development projects (experience delivering DDR/HBM IP is required).
• Must-have: Proficiency in logic design, digital simulation methodologies, and Verilog RTL development.
• Must-have: Strong knowledge of IC design flows and practical silicon experience; demonstrated completion of 10+ design projects as an individual contributor.
• Must-have: Familiarity with JEDEC-DDR/HBM, DFI and AMBA protocols and hands-on DDR project experience.
• Must-have: Strong verbal and written communication skills in English; ability to work effectively in a team and lead design activities.
• Nice-to-have: Experience with memory PHY timing closure, signal integrity, or hardware bring-up.

Education Requirements

Candidates typically hold a BS degree (electrical engineering, microelectronics, engineering science, or solid state physics) with ~6–10+ years of applicable experience, or an MS degree in those fields with ~3–7+ years of applicable experience, as stated in the posting.

About the Company

Company: Cadence Design Systems

Headquarters: San Jose, California, USA

Cadence Design Systems is a global electronic design automation company that provides software, hardware, and intellectual property for designing advanced semiconductor chips. With over 25 years in the industry, Cadence is known for its innovative technology solutions and has been recognized by Fortune Magazine as one of the 100 Best Companies to Work For. The company is dedicated to solving complex technical challenges in order to enable customers to create revolutionary products and experiences.