Lead ASIC Verification Engineer

Job Title

Lead ASIC Verification Engineer

Role Summary

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD CF IP's, ensuring no bugs are present in the final design.

Experience Level

Preferred experience includes proficiency in IP-level ASIC verification and debugging RTL code using simulation tools, with an understanding of UVM concepts and SystemVerilog language.

Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Estimate the time required to write new feature tests and changes to the test environment.
• Build directed and random verification tests.
• Debug test failures to determine the root cause; collaborate with RTL and firmware engineers to resolve design defects.
• Review functional and code coverage metrics; modify or add tests or constrain random tests to meet coverage requirements.

Requirements

• Proficient in IP level ASIC verification.
• Experience with Verilog, System Verilog, C, and C++.
• Skilled in using UVM testbenches and working in Linux and Windows environments.
• Experience developing UVM-based verification frameworks and automating workflows in a distributed compute environment.
• Exposure to leadership or mentorship is an asset.

Education Requirements

Bachelors or Masters degree in computer engineering or Electrical Engineering.