Layout Design Engineer

Job Title

Layout Design Engineer

Role Summary

The Layout Design Engineer is responsible for performing cell and chip-level schematic entry, IC layout, and verification including LVS, DRC, and ERC. This role includes collaborating with design engineers to prepare IC layouts for tapeout on various technologies while ensuring adherence to design verification standards.

Experience Level

Professional

Responsibilities

• Perform cell and chip-level schematic entry, IC layout, and verification (LVS, DRC, ERC).
• Chip floorplanning and I/O ESD routing, support/assist in tapeout and documentation.
• Collaborate with design engineers to prepare IC layouts for tapeout on CMOS, SOI, SiGe, and BICMOS technologies.
• Manage design databases using revision control systems.
• Create necessary documentation.
• Modify PDK and develop SKILL scripts to support CAD teams in layout flows.

Requirements

• BS Degree in Electrical Engineering, Computer Science, or equivalent.
• Knowledge of semiconductor technology and layout verification.
• Understanding of layout implementation flow and IC Design Methodologies using Cadence Virtuoso.
• Commitment to quality and support of R&D efforts.
• Relevant experience and willingness to learn.
• Experience with EDA tools such as Cadence Virtuoso, Assura, PVS, and Calibre.
• Familiarity with Linux and Windows systems.
• Proficiency in Linux shell scripts, SKILL, AMPLE, Perl, and Python is a plus.
• Able to work independently and within a team.
• Excellent communication and troubleshooting skills.

Education Requirements

BS Degree in Electrical Engineering, Computer Science, or similar field.