IP Verification Engineer

Role Summary

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s graphics processor IP, resulting in no bugs in the final design.

Experience Level

The candidate should have a solid background in digital design and verification with a passion for modern, complex processor architecture.

Responsibilities

Key responsibilities include:

• Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues.
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.

Requirements

The following skills and experiences are preferred:

• Proficient in IP level ASIC verification and debugging firmware and RTL code using simulation tools.
• Experience with UVM testbenches in Linux and Windows environments.
• Knowledge of Verilog, System Verilog, C, and C++.
• Familiarity with graphics pipelines and designing UVM based verification frameworks.
• Strong background in C++ on Linux and some experience with Windows.
• Knowledgeable in SystemC and TLM with some hands-on experience.
• Scripting experience: Perl, Ruby, Makefile, or shell preferred.
• Experience in leadership or mentorship roles is an asset.
• Familiarity with video codec systems or multimedia solutions is desirable.

Education Requirements

Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is required.