IP Verification Engineer

Role Summary

The IP Verification Engineer will be responsible for planning, building, and executing the verification of new and existing features for AMD’s graphics processor IP, ensuring high reliability in the final design.

Experience Level

This position is suitable for candidates with a solid background in processor architecture, digital design, and verification, with a strong focus on collaboration and problem-solving.

Responsibilities

The responsibilities include:

• Collaborating with architects, hardware engineers, and firmware engineers to understand new features for verification.
• Building test plan documentation that considers interactions with features, hardware, firmware, and software driver use cases.
• Estimating time for writing tests and necessary modifications for the test environment.
• Creating both directed and random verification tests.
• Debugging test failures and collaborating with RTL and firmware engineers to resolve design defects.
• Reviewing functional and code coverage metrics and adjusting tests to meet these metrics.

Requirements

Candidates must demonstrate the following:

• Proficiency in ASIC verification at the IP level.
• Experience in debugging firmware and RTL code using simulation tools.
• Competency with UVM test benches and familiarity with operating in both Linux and Windows environments.
• Proficient in Verilog, System Verilog, C, and C++.
• Experience developing UVM-based verification frameworks.
• Ability to automate workflows in a distributed computing environment.
• Previous exposure to the complete verification cycle from planning to sign-off.
• Preferred knowledge of DRAM protocol and PHY verification experience.
• Experience with AMS and GLS may be advantageous.

Education Requirements

A Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering is required.