IP Verification Engineer

Role Summary

As a verification engineer in the AECG Group, you will work on cutting-edge FPGA and ASIC designs for various customers. Your role involves close collaboration with architecture, IP design, PD teams, and product engineers to achieve successful silicon outcomes.

Experience Level

Level - Mid-Career

Responsibilities

• Collaborate with architects, hardware engineers, and firmware engineers to verify new features.
• Develop comprehensive test plans considering interactions with hardware, firmware, and software drivers.
• Code IP or SS level UVM-based testbenches and verification components including monitors, scoreboards, and checkers.
• Create directed and random verification tests.
• Run regressions and debug test failures to ensure high design quality and performance.

Requirements

• Education Requirements: Bachelor’s or Master’s degree in Computer Engineering or Electrical Engineering.

• Proficient in IP level ASIC verification.
• Expert in Verilog, System Verilog, and Object-Oriented programming.
• Experience in developing UVM-based verification frameworks and testbenches.
• Comfortable with scripting and automation of verification processes.
• Familiarity with simulation profiles, efficiency improvement, and HLS tools.
• Good understanding of computer architecture and systems.
• Knowledge of Python or Perl for maintaining scripts.
• Experience leading or mentoring others is advantageous.
• Experience through the ASIC project lifecycle from planning to tape-out.
• Familiarity with PCIe, CXL, NVMe, or Ethernet protocols is a plus.
• Strong communication skills and ability to work in a cross-site team environment.