IP/Subsystem - RTL Design Lead

Role Summary

As a member of the Computing and Graphics Group, you will help bring to life cutting-edge designs and contribute to achieving first pass silicon success in collaboration with various teams.

Experience Level

8-12 years full-time experience in IP hardware design.

Responsibilities

• Design of IP and subsystems with integration of AMD and other 3rd party IPs.
• Perform quality checks (lint, CDC, and power rule checks) of power-gated digital designs.
• Collaborate with the IP team to support design verification, implementation (synthesis, constraints, static timing analysis), and delivery to SOC.
• Partner with SOC teams for IP support at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up.

Requirements

• Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs.
• Familiarity with verilog lint tools (Spyglass) and verilog simulation tools (VCS).
• Experience with Clock domain crossing (CDC) tools.
• Detailed understanding of SoC design flows and IP/SS/SoC Power Management techniques (Power Gating, Clock Gating).
• Experience with embedded processors and data fabric architectures (NoC).
• Outstanding problem-solving and analytical skills.
• Effective communication skills in both verbal and written formats and ability to collaborate with global teams.

Education Requirements

• Bachelor's degree in Computer Engineering/Electrical Engineering plus 12 years full-time experience in IP hardware design, or a Master's degree plus 8 years experience in the same field.