IP Power Engineer

Role Summary

AMD is seeking a highly skilled and motivated IP Power Engineer to join our MMHUB/ATHUB IP design team. In this role, you will be responsible for developing and implementing power management solutions for cutting-edge IP blocks used in AMD's high-performance products. You will work on power optimization, analysis, and verification to ensure our products meet stringent power, performance, and area (PPA) targets.

Experience Level

Level - Mid-Career

Responsibilities

• Develop power intent specifications using industry-standard formats (UPF/CPF)
• Create and optimize power domains, power gating strategies, and voltage/frequency scaling techniques
• Collaborate with RTL design teams to implement low-power design techniques at the microarchitecture level
• Perform static and dynamic power analysis using industry-standard tools (PrimeTime PX, Voltus, PowerArtist, etc.)
• Conduct power profiling and identify power optimization opportunities across different use cases and workloads
• Analyze power consumption trends and provide recommendations for power reduction
• Develop and maintain power models for early-stage power estimation
• Debug power-related issues in RTL, gate-level, and post-silicon environments
• Collaborate with DV teams to ensure power scenarios are adequately covered in functional verification

Requirements

• Education Requirements: Masters degree in computer engineering/Electrical Engineering

Preferred Experience

• Strong understanding of digital design fundamentals technology. Knowledge of advanced process nodes (7nm, 5nm, 3nm and beyond)
• Proficiency in hardware description languages (Verilog, SystemVerilog, VHDL)
• Experience with UPF (Unified Power Format) and power-aware design flows
• Familiarity with power analysis tools (Synopsys PrimeTime PX, Cadence Voltus, or similar)
• Knowledge of power management techniques: clock gating, power gating, multi-voltage design, DVFS
• Understanding of static and dynamic power consumption mechanisms
• Experience with scripting languages (Python, Perl, TCL, Shell) for automation
• Experience with machine learning or AI-based power optimization techniques
• Background in physical design and understanding of power delivery networks
• Experience with post-silicon power characterization and debug