IP Design Verification Engineer

Role Overview

The IP Design Verification Engineer will be responsible for planning, building, and executing verification processes for AMD’s AXI HUB IP. The objective is to ensure that both new and existing features are free of bugs, contributing to a high-quality final design.

Role Summary

This role involves close collaboration with architects and hardware engineers to verify new features, developing comprehensive test plans, and debugging test failures to coordinate with RTL engineers effectively.

Experience Level

Level - Mid-Career

Responsibilities

• Collaborate with team members to understand features requiring verification.
• Create test plans that address feature interactions and hardware use cases.
• Estimate time requirements for test writing and necessary adjustments to the testing environment.
• Develop both directed and random verification tests.
• Analyze test failures to identify root causes and work with RTL engineers to resolve issues.
• Review functional and code coverage metrics, modifying tests to meet established coverage requirements.

Requirements

• Proficiency in IP-level ASIC verification and debugging RTL code.
• Experience with UVM testbenches and working knowledge of both Linux and Windows environments.
• Familiarity with Verilog, System Verilog, C, C++, and knowledge of AXI protocols.
• Experience in developing UVM based verification frameworks and workflows in distributed environments.
• Practical knowledge of SystemC, TLM, and scripting languages such as Perl or Ruby.
• A preferred background in leadership or mentorship roles and familiarity with multimedia solutions.

Education Requirements

A Master’s degree in Computer Engineering or Electrical Engineering is required.