Interconnect Micro-architect/RTL Design Engineer

Role Summary

The Interconnect Micro-architect/RTL Design Engineer will join the Infinity Fabric Architecture and RTL team to develop the next generation of coherent interconnects. This position offers the unique opportunity to work on a variety of market-driven products including traditional servers, high-performance computing solutions, PCs, and embedded applications.

Experience Level

This role is suitable for experienced RTL design engineers possessing strong communication skills and a passion for complex processor architectures and digital designs.

Responsibilities

The key responsibilities of this position include:

• Conducting early architectural and performance exploration through micro architectural definitions and designs.
• Optimizing designs to meet power, performance, area, and timing requirements.
• Writing synthesizable and easily readable Verilog RTL.
• Performing unit level testing to ensure high-quality code delivery to the Design Verification Team.
• Creating assertions and analyzing design coverage for complete verification.
• Documenting block-level designs comprehensively.
• Engaging in post-silicon functional and performance debugging and tuning.

Requirements

Successful candidates will demonstrate:

• Proven experience in designing logic blocks for CPU, GPU, NOC, or cache systems.
• Expertise in Verilog and System Verilog.
• Familiarity with C, C++, and scripting languages such as Perl or Python.
• Comprehensive understanding of digital electronics, including high-speed designs exceeding 1GHz.
• Knowledge of multi-processor coherency, memory and I/O ordering, interrupts, MMU, and caches.
• Strong debugging and analytical capabilities.
• Exposure to Design for Test principles, including scan concepts and DFT-friendly RTL design.
• Experience with x86 or ARM ISA is advantageous.

Education Requirements

A BS, MS, or PhD degree in Electrical or Computer Engineering is preferred.