HW Release Intern

Role Summary

This internship at Synopsys involves practical engagement in the development and verification process of hardware components, primarily focused on DDR/HBM/UCIE PHY elements.

Experience Level

Applicants should be degree-seeking students or recent graduates in Computer or Electrical Engineering, preferably from the 2023 or 2024 graduating class.

Responsibilities

• Build and verify components for DDR/HBM/UCIE PHY.
• Execute synthesis, RTL and gate-level simulation, while debugging failures encountered.
• Gather statistics on design and verification issues to identify critical areas needing improvements.
• Contribute to the automation processes in the Release flow as needed.

Requirements

• Must be enrolled in or have graduated from a Computer or Electrical Engineering program.
• Familiarity with UNIX/Linux operating systems is essential.
• Knowledge of design models such as GDSII, LEF, LIB, and Verilog.
• Understanding of both analog and digital design flows.
• Experience with scripting languages (Python, Perl, bash, TCL) is preferred.
• Basic familiarity with Synopsys tools is advantageous.
• Previous work in IC design and verification is a plus.
• Strong English verbal and written communication skills are required.
• Must be responsible, detail-oriented, and self-motivated.
• Ability to learn quickly and handle multiple tasks under time pressure.
• Proficient organizational and problem-solving abilities.

Education Requirements

Enrolled in or graduated from an accredited Computer or Electrical Engineering degree program.