HSIO DFT Lead Verification Engineer

Role Summary

We are looking for an adaptive, self-motivated DFT design verification engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry-leading technologies to market.

Experience Level

Level - Mid-Career

Responsibilities

Key responsibilities include:

• Design verification of PCIe, UCIe, Chiplet Interconnect IPs for Analog/HSIO DFx features
• Build testbench components to support the next generation of NBIO IPs
• Estimate the time required to write the new feature tests and any required changes to the test environment
• Develop, maintain, and improve test libraries to support IP level testing
• Test coverage and test cost reduction analysis
• Train and mentor junior team members for PRBS DV execution
• Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning

Requirements

Preferred qualifications include:

• Understanding of Design for Test methodologies and DFT verification experience (e.g. JTAG 1149.x, IJTAG, PRBS, IO Loopback, etc.)
• Experienced with Verilog, System Verilog, C, and C++
• Development of UVM based verification frameworks and testbenches, processes and flows
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
• Debug test failures to determine the root cause; work with design engineers to resolve design defects and correct any test issues
• Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test and characterization
• Design verification experience of High-Speed IO PHY and Controller logic is preferred

Education Requirements

Bachelor’s or master’s degree in related discipline preferred.