High Speed Serdes PHY Application Engineer

Job Title

High Speed Serdes PHY Application Engineer

Role Summary

This role involves the entire SoC design flow from architecture, high-speed Interface IP (IIP) integration, synthesis, design for test (DFT), low power design (UPF), CDC/RDC check, static timing analysis (STA), silicon test plan, silicon bring-up, and mass production silicon debug.

Experience Level

Minimum 5 years of Analog or Mixed signal IP or ASIC Design/Verification/Applications experience is required.

Responsibilities

• Work closely with customers to understand new requests or customization features from customer’s PRD/MRD.
• Provide integration training to customers and conduct reviews on their major SoC milestones.
• Provide feedback to Synopsys R&D for customization features or continuous IIP product improvements.
• Participate in IIP design reviews to align development with future customer needs.
• Develop tools to simplify daily tasks or improve efficiency; author application notes for gate-level simulation, silicon debug, and physical implementation.

Requirements

• Bachelor’s and/or master’s degree in Electrical and/or Electronic Engineering, Computer Engineering, or Computer Science.
• Hands-on experience in circuit design, RTL coding, simulation, synthesis, static timing check, equivalence check, etc.
• Domain knowledge of PCI Express, CXL, and Ethernet protocols.
• Strong verbal and written communication skills in English, with the ability to interact with customers.
• High degree of self-motivation and personal responsibility.
• Excellent problem-solving skills and attention to detail.

Education Requirements

Bachelor’s and/or master’s degree in Electrical and/or Electronic Engineering, Computer Engineering, or Computer Science.