Hardware Integration Engineer

Role Overview

The Hardware Integration Engineer is responsible for developing and maintaining verification tests for core and IP levels, contributing to the evaluation of AMD's cutting-edge technologies. This position requires collaboration with cross-functional teams to ensure high-quality outcomes in a dynamic environment.

Professional Level

This position is intended for mid-career professionals with a strong background in design verification engineering.

Key Responsibilities

• Develop and maintain tests for functional and performance verification at core and IP levels.
• Build and enhance testbench components for next-generation IP.
• Maintain and improve existing test libraries to enable robust IP-level testing.
• Create hardware emulation builds to verify IP functionality and performance.
• Enhance the hardware emulation environment for improved runtime performance and debugging.
• Provide technical support across cross-functional teams.
• Contribute to RTL design and support implementation through the complete physical design flow.
• Perform static timing analysis (STA), EMIR, and power integrity checks.
• Support physical implementation from RTL through GDS, encompassing timing, EMIR, and necessary signoff analyses.

Key Requirements

Experience in C/C++, familiarity with SystemVerilog, and modern verification methodologies such as UVM are required. Hands-on experience with RTL design and physical implementation to GDS is necessary, as well as integration with STA, EMIR, and PNR tools.

Education Requirements

A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field is required.