The Memory IO team at AMD is seeking an experienced Hardware Development Engineer to lead RTL and Firmware development for high-speed LPDDR, DDR, and inter-chip I/O IPs. This role involves defining, designing, and developing industry-leading Memory PHYs and interface IPs.
Candidates should possess strong analytical skills, detail orientation, and a self-starter attitude with a demonstrated ability to drive tasks to completion. Experience in a team-oriented environment with effective communication skills is essential.
Applicants should have experience in digital design engineering with a focus on successful tape-outs and technical leadership. Proficient knowledge of Verilog, C, C++, and scripting languages such as Python, Perl, and TCL is required. Familiarity with clocking architectures, synchronization, and CDC methodology is essential. Prior experience with DSP, control theory, and algorithms is preferred, along with knowledge of SERDES, DDR, Memory Controller, or MAC design.
A Bachelor's degree in Electrical or Computer Engineering is required; a Master's or PhD degree will be considered an advantage.