General RTL Engineer

Role Summary

The General RTL Engineer will work on SOC and processor design within a small, experienced team, contributing significantly to the design process.

Experience Level

Mid-level with significant experience in RTL design.

Responsibilities

The candidate will be expected to:

• Develop RTL designs with a focus on micro-architecture, pipelining, timing closure, power, and area optimization.
• Work with memory interfaces, bus interfaces, and integrate IPs and glue-logic.
• Collaborate with Architecture, Verification, and Physical Design teams.

Requirements

Must-have skills include:

• Strong background in RTL design.
• Experience in micro-architecture development and timing closure.
• Knowledge of IOs and memory interfaces.

Nice-to-have skills:

• Experience in glue-logic development.

Education Requirements

Not specified.

About the Company

Company: Akeana

Headquarters: Santa Clara, CA, USA

Akeana is a start-up specializing in processor design, with a team experienced in developing state-of-the-art products. Their expertise spans multiple architectures, including Risc-V, ARM, and x86, with backgrounds from prominent companies in the semiconductor industry. Funded by top-tier venture capitalists and industry leaders, Akeana focuses on innovative RTL design and micro-architecture development.