Front End Design - STA Engineer

Role Summary

This position involves responsibility for developing low-power design strategies, synthesis, and timing closure for complex SoC and IP designs using EDA tools.

Experience Level

Entry to mid-career level candidates are encouraged to apply. Strong experience with ASIC synthesis and STA is preferred, but recent graduates with relevant skills may also be considered.

Responsibilities

The key responsibilities include:

• Developing and implementing power reduction strategies across SoC/IP design.
• Performing synthesis and static timing analysis (STA) to achieve PPA targets.
• Analyzing and optimizing dynamic and leakage power using EDA tools.
• Collaborating with RTL designers, physical design, and verification teams to meet timing and power requirements.
• Running low-power verification checks (UPF/CPF) and validating power intent implementation.
• Supporting sign-off activities for synthesis, timing, and power closure.
• Automating power and timing workflows to enhance efficiency.
• Building test plan documentation for hardware interactions.

Requirements

Applicants should have a strong background in ASIC synthesis and static timing analysis, as well as hands-on expertise with EDA tools such as Synopsys. Understanding of power optimization techniques and familiarity with UPF/CPF is beneficial. Knowledge of digital design fundamentals and proficiency in scripting languages for automation are also important.

Education Requirements

A Master’s degree is preferred, but candidates with a Bachelor’s degree are equally welcome to apply.